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LNK3694G design with EE13 core

Posted by: DariusP on 10/11/2022



Using LNK3694G part with EE13 size transformer. Overall design works but during operation I've observed high Vds peak voltages (possibly due to leakage inductance?).

Any recommendations for transformer winding/layout adjustment to reduce leakage inductance? Would bias-sec-pri or pri-bias-sec would reduce leakage inductance significantly ?


In existing design replaced RC clamp with zener diode, so it limits peak Vds voltages to safe with some margin.

In-depth EMI measurements haven't been performed, but quick PPEAK scan indicates no issues. Also tried bias-pri-sec layout for transformer, it has lower leakage inductance but due to high primary winding count bias-sec coupling is weak and without optocoupler output regulation is very poor.

Attached PIXI sheet for initial transformer calculation and actual implementation in design. I've adjusted winding placement for better bias coupling to secondary.

Maybe you have some other suggestions to improve design ?



Submitted by PI-Wrench on 10/12/2022

Standard procedure for reducing leakage inductance is to sandwich the secondary and bias windings between two halves of a split primary, like so:

1/2 primary - bias - secondary - 1/2 primary.

This will reduce the leakage inductance and make the primary snubber more effective. Remember also to include a Y1 capacitor (0.5 - 1 nF is a good starting value) between secondary return and either B+ or primary return, whichever works better in an EMI scan. This provides a return path for common mode noise coupled between primary and secondary via the transformer interwinding capacitance.